1. Technical Field
The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk effects in the interface device by using information stored in an integrated circuit attached to that interface device. .
The present invention is particularly applicable to interfaces to logic and memory devices, to test equipment for testing semiconductor devices and to high speed communications.
2. Background of the Invention
It shall be appreciated that the invention can be applied to a wide variety of fields, though examples and background information, without limitation to the scope of the invention, represent automated semiconductor testing. Test equipment is typically used to determine whether a device under test (“DUT”) follows a set of timing specifications. Accordingly, timing accuracy plays a vital role in the design of test equipment because a discrepancy in the timing accuracy can result in an incorrect classification of a DUT.
A typical test equipment comprises a tester and a device interface board (DIB) connected thereto. A test socket adapted to receive a DUT is mounted on the interface board. A plurality of transmission lines such as coaxial cables or strip lines are provided which join contacts of the test socket and junctions of the interface board with the testing device. The tester and the interface board are interconnected by urging pin electrodes provided on one of them against planar electrodes provided on the other, by pressing planar electrodes provided on both of them against each other, or by engaging connectors provided on both of them with each other. A device to be tested is mounted on the test socket.
A signal generator in the tester generates a test signal of logical levels at specified timings, based on a pattern and a timing signal. The test signal is converted by a driver in the tester into a signal voltage of a predetermined level such as the ECL or TTL level, which is supplied from the tester to pins of the DUT via the transmission lines of the interface board. Then, the resulting DUT output response signals are provided via the transmission lines to the tester, wherein they are compared by a comparator with a reference voltage for the decision of their logical level. Each logical signal based on the decision is compared by a logical comparator with an expected value pattern contained in the data pattern, and the output from the logical comparator is used to determine whether the DUT is good or bad.
In this instance, it is necessary that the timing for sending out the test signal and the timing for fetching the DUT output response signal in the tester be determined taking into account not only the relative delay times between respective circuits in the tester corresponding to the pins of the DUT or delays in the transmission lines but also crosstalk or crosstalk artifacts times of the transmission lines of the interface board which are connected to the pins of the DUT.
The following methods have been proposed to adjust the test signal send-out timing and the DUT output response signal acquisition timing.
According to one of these methods, the transmission lines are made equal in length to make the above-mentioned delay times in the interface board constant, and in the tester, the above-said timing is corrected using data on the constant time. This method suffers from differences between the physical length—all wires are normally the same actual length, and the electrical length for a given pattern. According to another method, the actual lengths of the transmission lines and the delay times are measured, the measured data are stored in a memory provided in the tester and the above-said timing is adjusted using the data read out of the memory. This method tries to adjust delay times by measuring the electrical length of isolated traces. In practice, the electrical length is influenced heavily by crosstalk, so the electrical length during measurement is not an accurate representation of the electrical length in service.
According to still another method, such as described in U.S. Pat. No. 5,225,775, the DUT connection board is equipped with a nonvolatile storage for storing data on the delay times in the transmission line on the connection board corresponding to each terminal of the device under test, and the tester main body unit is so constructed as to adjust the test signal send-out timing and the device output response signal acquisition timing based on the data read out of the storage. Storing the actual topography and topography dependent parameters in a serial presence detect (SPD) memory and adjusting a control signal accordingly is known also from U.S. Pat. No. 6,321,282. This suffers the same problems as previously mentioned, i.e. the electrical length during isolated test differs from that in service due to the neglect of the crosstalk coefficients.
According to U.S. Pat. No. 5,225,775, a calibration procedure is performed by selecting one of a plurality of transmission lines on the connection board and measuring a time required for a signal to pass via this connection board, while all the other transmission lines are silent. Thus, cross-talk from adjacent lines is not taken into account.
As the speeds at which electronic devices operate have increased dramatically and it is not uncommon for these memory devices to run at frequencies at or greater than 100 MHz, the above mentioned methods fails to provide an adequate accuracy of timings. To test at such high frequencies, tester systems include a clock running at or above the maximum frequency at which devices can be tested. As clock frequencies increase, factors such as transmission line crosstalk or crosstalk artifacts such as uneven transmission line performance become significant. To compensate for such variations, some tester systems, such as production-oriented automatic test equipment (ATE) testers, use very high frequency (some as high as 1 GHz) to provide very fine resolutions. However, in these systems crosstalk in signal paths can influence greatly the accuracy of calibration.
Still one more problem arises when the number of testing signals required to test a semiconductor device increases and it becomes more and more complicated technically to compensate timing errors for individual signals in each separate transmission line.
The similar problems arise in high speed communications where it is required to reduce artifacts introduced into a communication channel from the limited and non-linear characteristics of the channel, such as by reflections not being absorbed efficiently or cross-talk between the transmission lines.